1. Field of the Invention
The present invention relates to a semiconductor integrated circuit operable under circumstances where a plurality of supply voltages are coexistent, as in an instance where the integrated circuit is mounted on a board which is so designed as to operate with a power source including a plurality of supply voltages, and/or bearable against live disconnection.
2. Description of the Prior Art
In respect of designing a circuit board, there is recently adopted a technique of reducing a supply voltage to, e.g., 3 V for some partial devices while applying 5 V to operate the other devices. In most cases, the reason is based on an attempt to realize suppression of the entire power consumption or on the specification that the rated supply voltage for some partial devices is lower than 5 V. Under such circumstances where mutually different supply voltages are coexistent for the individual operations, there may arise a problem that, when a signal is fed from a 5 V device to a lower-voltage device or the devices operated at mutually different voltages are connected to the same bus, a current flows from the 5 V device to the lower-voltage device. Such an undesired current flow may cause considerable disadvantages including an increase of the power consumption, latch-up of the devices and, due particularly to the voltage of 5 V, breakdown of transistors in the latest miniaturized high-density devices.
FIG. 9 typically shows how a 3 V-operated device and a 5 V-operated device are coexistent on a board while being connected to a common bus, and FIG. 10 is a schematic circuit diagram of a known conventional bi-directional buffer circuit enclosed with a circle in FIG. 9.
When a 3 V device and a 5 V device are connected to a common bus as shown in FIG. 9, there arise the following problems (1) to (3) in the circuit of FIG. 10.
(1) Upon input of 5 V from an external bus 10 via a pad 11, a parasitic diode 12a for a P-channel transistor 12 in the final output stage is turned on to consequently form a current path (1), whereby a great leakage current is caused to flow therethrough.
(2) Since merely 3 V is applied to the gate of the P-channel transistor 12, this transistor 12 fails to be completely turned off and is therefore placed in a weak on-state, so that a current path (2) is formed therein also.
(3) As 5 V is applied to both an N-channel transistor 13 in the final output stage and an N-channel transistor 14 in the initial input stage, a high electric field is generated to eventually arouse some problems relative to the withstand voltage of gate oxide films, hot carriers and so forth, whereby the N-channel transistors 13 and 14 may be broken down.
FIG. 11 typically shows conventional means contrived for solving the problems mentioned above. In this diagram, there is included merely its output buffer circuit alone.
For the purpose of preventing a leakage current when the supply voltage is 5 V with regard to the bus 10 on the board, 5 V is applied to the final output stage. Further, the oxide film of the transistor only in the final output stage is processed to be thicker so that this transistor may not be deteriorated even if 5 V is applied to the final output stage. In addition to such countermeasures, a level shift circuit for converting a 3 V signal into a 5 V one is incorporated to achieve complete turn-off of the P-channel transistor in the final output stage, wherein a 3 V signal in a 3 V system circuit is converted into a 5 V signal, which is then supplied to the gate of the P-channel transistor in the final output stage.
As a result of the means mentioned, there is contrived an improved circuit system where both a 3 V-operated device and a 5 V-operated device are rendered connectable to the common bus 10.
However, for effecting the measures shown in FIG. 11, it is unavoidable that some processing steps are increased inclusive of forming a thicker oxide film only partially, and a longer time is required for manufacture of a chip to eventually bring about a rise of the production cost.
Furthermore, it becomes necessary to supply voltages of two systems, i.e., 3 V and 5 V, to the devices to consequently induce additional complication of the wiring on the board with a disadvantageous increase in the number of required pins on the chip.
In Japanese Patent Laid-open No. Hei 4 (1992)-290008, there is disclosed an off-chip driver circuit which comprises a single pull-up transistor; an output terminal; a voltage source for providing a supply voltage of a predetermined value in an arrangement where the pull-up transistor is disposed between the voltage source and the output terminal; a control transistor connected between the gate electrode of the pull-up transistor and the output terminal, and having a gate electrode connected to a first reference potential point; a bus gate; a predriver circuit coupled via the bus gate to the gate electrode of the pull-up transistor; and means for selectively applying to the output terminal a voltage considerably higher than the aforesaid supply voltage of a predetermined value.
However, this known driver circuit also has some disadvantages that, since the substrate (back gate) of the pull-up transistor is biased from the power source via the control transistor, the back gate resistance is rendered high and therefore a latch-up problem is prone to be raised.
Further, when a partial circuit board is inserted into and/or extracted from a connector of a main system without cutting power supply thereof, voltage may be applied to the pad without supplying voltage to the output buffer circuit due to disconnection of the connector. Also in this live disconnection case, the same current paths (1) (2) as shown in FIG. 10 cause in prior art output buffer circuit. So, there is a problem in a reliability.
More specifically, when "H" is inputted to the pad 11 through connector pin under the condition that power supply 3 V to the last stage transistor 12 is cut down (off) to 0 V, currents (1) (2) as shown in FIG. 10 flow within transistor 12 so that parasitic diode 12a and then transistor 12 turned on.